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Research paper published in Nano Letters 2008, Volume 8, Issue 8, pp. 2437–2441, July 18, 2008.
F A Ghavanini, H Le Poche, J Berg, A M Saleem, S Kabir, P Lundgren, P Enoksson • July 18, 2008
We comÂpare the levÂel of deteÂriÂoÂraÂtion in the basic funcÂtionÂalÂiÂty of indiÂvidÂual tranÂsisÂtors on ASIC chips fabÂriÂcatÂed in stanÂdard 130 nm bulk CMOS techÂnolÂoÂgy when subÂjectÂed to three disÂparate CVD techÂniques with relÂaÂtiveÂly low proÂcessÂing temÂperÂaÂture to grow carÂbon nanosÂtrucÂtures. We report that the growth techÂnique with the lowÂest temÂperÂaÂture has the least impact on the tranÂsisÂtor behavior.
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