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Research paper published in the proceedings of 2nd PCNS Passive Components Networking Symposium, Bucharest, Romania, 10–13 September, 2019. Award for outstanding paper.
R Andersson, M Bylund, S Krause, A M Saleem, V Desmaris • October 26, 2019
ComÂplete on-chip fulÂly solÂid-state 3D inteÂgratÂed capacÂiÂtors using verÂtiÂcalÂly aligned carÂbon nanofibers as elecÂtrodes to proÂvide a large 3D surÂface in a MIM conÂfigÂuÂraÂtion have been manÂuÂfacÂtured and charÂacÂterÂized. The capacÂiÂtance per device footÂprint area has been studÂied, as well as its behavÂior at difÂferÂent temÂperÂaÂtures and freÂquenÂcies. EquivÂaÂlent series resisÂtance (ESR), breakÂdown voltÂage and leakÂage curÂrent have also been meaÂsured. The entire manÂuÂfacÂturÂing process of the capacÂiÂtors is comÂpleteÂly CMOS comÂpatÂiÂble, and in comÂbiÂnaÂtion with the low device proÂfile of about 4 µm this makes the devices readÂiÂly availÂable for inteÂgraÂtion on a CMOS-chip, in 3D stackÂing, or redisÂtriÂbÂuÂtion layÂers in a 2.5D interÂposÂer techÂnolÂoÂgy. CapacÂiÂtances of ca 350 nF/​mm2, ESR of about 100 mΩ, breakÂdown voltÂages of up to 25 V and leakÂage curÂrents in the order of 0.004 nA/​nF have been measured.
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